Bio
Dr. Limbrick is an Associate Professor in the Electrical and Computer Engineering Department at NC A&T. As a postdoctoral fellow at the Georgia Institute of Technology, he researched methods to improve routing congestion in monolithic 3D integrated circuits with Dr. Sung Kyu Lim. As a doctoral student, Dr. Limbrick was a member of the Radiation Effects and Reliability (RER) Group and the Security And Fault Tolerance (SAF-T) Research Group, where his research was conducted under the advisement of Dr. William H. Robinson. He received a BS degree in Electrical Engineering at Texas A&M and his MS degree and Ph.D. degree at Vanderbilt University.
Research Interests
Dr. Daniel B. Limbrick leads the Automated Design for Emerging Processing Technologies (ADEPT) Laboratory at NC A&T where he researches ways to improve the reliability and scalability of integrated circuits through logic & physical synthesis. His research interests include electronic design automation, post-CMOS technologies, computer architecture, lab-on-a-chip, and the reliability of microelectronics.
External URL
Recent Publications
- Bradley Kiddie, William Robinson, Daniel Limbrick, Bradley Kiddie, Daniel Limbrick (2015). (Single-Event Multiple-Transient Characterization and Mitigation via Alternative Standard Cell Placement Methods). (4) 20, pp. 60:1 - 60:22 ). ACM Trans. Des. Autom. Electron. Syst..
- D. Black, W. Robinson, I. Wilcox, Daniel Limbrick, J. Black, D. Black, Daniel Limbrick (2015). (Modeling of Single Event Transients With Dual Double-Exponential Current Sources: Implications for Logic Cell Characterization). (4) 62, pp. 1540-1549 ). IEEE Transactions on Nuclear Science.
- , Daniel Limbrick, Daniel Limbrick (2013). (Reliability-Aware Synthesis of Combinational Logic With Minimal Performance Penalty). (4) 60, pp. 2776 - 2781 ). IEEE Transactions on Nuclear Science.
- Nihaar Mahatme, Indranil Chatterjee, Akash Patki, Daniel Limbrick, Bharat Bhuva, Ronald Schrimpf, William Robinson, Nihaar Mahatme, Daniel Limbrick (2013). (An efficient technique to select logic nodes for single event transient pulse-width reduction). (1) 53, pp. 114 - 117 ). Microelectronics Reliability.
